1. Field of the invention
This invention relates to integrated circuit memories, and in particular, to an apparatus for providing redundant rows in such memories when other portions of the memory are found defective.
2. Description of the Prior Art
In integrated circuit memories, a single defect in any portion of the array of memory cells may render the entire memory useless. As improvements in the design and fabrication of integrated circuits are made, greater numbers of memory cells are being placed on a single chip. Furthermore, generally physically larger integrated circuits are being manufactured. Each factor tends to increase the likelihood of a defect in one or more cells which may render an entire chip useless.
One prior art solution to this problem has been to design and fabricate integrated circuit memories using more fault tolerant designs and processes. This approach, by itself, does not always suffice. Consequently, another solution which has received increasing attention is the fabrication of redundant components on the same chip. At a suitable stage in the fabrication process, the non-functional portions of the circuit are replaced with the redundant portions, typically by using redundant wiring techniques, fuses, discretionary metal masks, or other techniques. The usual prior art approach, however, has been to replace an entire relatively large block in the memory with a new block. For example, in a 64 k memory divided into 16 sections, each of 4 k bits, a defective bit in a single section will result in the replacement of the entire 4 k section. Unfortunately, this approach requires a considerable amount of extra logic and extra space on the integrated circuit.
While redundant rows improve yield, and are relatively simple to implement, the addressing scheme for redundant rows is critical because it lies along the critical signal path. The added decoding circuits for the redundant rows, when selected by laser fusing or other techniques, must select the redundant row and at the same time de-select all the other redundant rows and normal rows of memory cells. At the same time, the operating speed of the overall memory must not be affected by the added circuitry.